![]() ![]() ![]() This behaviour is a peculiarity of this series of op-amps and is plainly stated in the datasheet. The op-amp sees this as an input at the negative rail, not 4V above it and (BOOM) sends the output right up as close as it can get it to the positive rail. When you turn on the +ve rail only, the inputs and the negative rail is still pretty close to 0V. So, if an input goes MORE NEGATIVE than 4V above the -ve rail then the output can go to the positive rail. The valid range for this op-amp is guaranteed to be no worse than (from table 6.10) from -11V to +11V using a +/-15V rails. It states: "Avoid input voltage values below 1 V to prevent phase reversal where output goes high." This means that the output can go towards the positive rail even if the inputs might suggest it do otherwise, in the case that the inputs go outside of their valid range. Here is the datasheet for the TL071: Take a look at section 8.3.2. When you use an IC it is always a good idea to have a copy of its datasheet at hand. This is one of those details often skipped in university classes and intro textbooks that causes young engineers much stress in the real world. Power supply sequencing is itself a fairly large subject and can include limits on how long one supply can be up before the other, and ramp rates on the turn on. If your application requires the output to be maintained below a certain level you must control power supply sequencing, and possibly clamp the inputs and output by some means until the supplies are known to be up and stable. Your results are not surprising, but as others have said, might be totally different with another type of op amp, and possibly different with another sample of the same type. In your test case there is a complex (meaning there are multiple signal paths, some of which may involve diodes or transistors), probably high impedance path to ground through the 1.0 volt reference circuit. When specified voltages are applied the parasitic junctions are all properly biased to prevent any impact on operation and the circuit will work as designed. Not just the schematic of the op amp internals, but also all of the parasitic junctions that occur due to the fab process. The result lies in the details of the op amp implementation. There is no generic answer to your question. one between Vref and in+ and the other in the feedback loop, so the input bias currents for both in+ and in+ cause similar voltage drops). I would also recommend 10K resistors in series with each input (i.e. It will still misbehave, but usually less severely than if a rail is totally disconnected and floating. If you use mechanical or independent supply rail switching, or there is any other way one rail may become disconnected, even momentarily, it may be helpful to put reversed biassed diodes between both rails and ground so neither rail can be dragged past ground when it isn't powered. See OPAMP datasheet + any available manufacturer's application guides for that OPAMP, and consider carefully if the specified permissible input voltage range could be violated transiently during powerup or powerdown. if the absolute maximum input voltage range extends considerably beyond the rails, or if the input circuit has enough resistance to limit the input current enough to prevent damage. For specific OPAMPs and application circuits it may be permissible to apply signals before power. ![]() Also, no signals should be applied unless the operating voltages on the supply rails are present and stable. Generally, both supply rails of a dual supply OPAMP should always have their voltage applied (and removed) at the same time. You've got a power and signal sequencing problem. ![]()
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